Variable threshold level field effect memory device



United States atent Inventor Joseph H. Scott, Jr.

Newark, NJ.

Dec. 5, 1968 Dec. 22, 1970 RCA Corporation a corporation of DelawareAppl. No. Filed Patented Assignee VARIABLE THRESHOLD LEVEL FIELD EFFECTMEMORY DEVICE 5 Claims, 7 Drawing Figs.

[1.8. CI. 307/279, 307/205, 307/235. 307/251 i 307/304; 330/35 Int. Cl.H031: 17/60 Field of Search 307/205,

[56] References Cited UNITED STATES PATENTS 3,348,062 10/1967 Carlson etal 307/235 3,369,129 2/1968 Wolterman..... 307/304X 3,374,312 3/1968Thomas 307/304X 3,444,397 5/1969 Lym 307/304X 3,462,701 8/1969 Miller330/38(FE)X Primary Examiner-Stanley T. Krawczewicz Attorney-H.Christoffersen PATENTEU 052221970 INVENTON Mam! 1% Jam; fi.

BAA- W AT THEME Y OLDLEVELLDE 1 MEMORY navrcn BACKGROUND OF THEINVENTION Semiconductor active devices are of great interest for use asmemory elements. They are fast, inexpensive, require little power,occupy a small amount of space, and may be integrated to form largearrays. However, there is room for much improvement in a number ofareas. For example, commercially available storage circuits of this typegenerally employ a minimum of four or five elements such as transistorsor the like, for each bit of stored information. If the number ofelements per hit could be reduced to, for example, one transistor perbit, the number of storage cells which could be packed into a given areawould be increased correspondingly, by a factor of four or five.

A number of proposals have been made in the past to meet this need. Oneis the ferroelectric transistor. A ferroelectric transistor is asemiconductive body whose conduction path is altered by polarizing aferroelectric maintained in proximity to the body to alter the surfacecharge on a portion of that body. However, in practice such devices haveproved extremely difficult to manufacture and have been highly unstable.

Another deficiency of commonly employed semiconductor device storagecircuits is that any interruption or loss of power applied to thedevices causes the loss of the stored information.

It is an object of the present invention to provide a new and improvedactive element storage circuit which exhibits a reproducible and stablehysteresis loop as a function of applied voltage and which retains itsstored information whether or not power is present.

BRIEF SUMMARY OF THE INVENTION Circuits embodying the invention includea bistable field effect transistor having a source electrode, a drainelectrode and a gate electrode. The transistor is of the type which, inresponse to a first voltage of greater than a given value appliedbetween its gate and source electrodes in a direction to forward biasthe gate with respect to the source, exhibits a first threshold value,and which, in response to a second voltage of greater than a given valueapplied between its gate and source electrodes in a direction to reversebias the gate with respect to the source, exhibits a second thresholdvalue. Voltages are applied between the source and gate electrodes forselectively setting the threshold value of the transistor into one ofits two states. Sampling voltages are also applied to the gate electrodeto sense the state in which the transistor has been set. This providesnondestructive read-out of the information contained in the transistor.

BRIEF DESCRIPTION OF DRAWING FIG. I is a cross-sectional view of oneembodiment of the type of semiconductor device which may be used topractice the invention;

FIG. 2 is a plot of capacitance versus applied voltage illustrating thebistable character of the device;

FIG. 3 is a circuit diagram showing the device used as a variablethreshold detector;

FIGS. 4a and 4b are plots of the V-I characteristics of the device whenpulsed into the low and high threshold states;

FIG. 5 is a schematic diagram showing the device used as a singleelement memory device; and

FIG. 6 is a schematic diagram showing a series means to set and read outthe memory element of FIGS.

DETAILED DESCRIPTION FIG. I shows a depletion-type, insulated gate fieldeffect transistor 10 suitable for practicing the invention. Thetransistor It includes a body 12 of semiconductive material of givenconductivity type, such as P-type silicon, which has an upper surface M.Adjacent to the surface 14 are spaced regions l5 and 16 of conductivitytype opposite to that of body 12, which constitute source and drainregions, respectively, for the transistor 10. The distance betweenregions I? and T6 defines the width of the conduction channel. ContactsId and 20 are formed on the surface 14 in ohmic contact with the regionsl5 and I6.

Overlying the channel space between the regions 15 and I6 is a structurewhich comprises the gate and charge-storing elements of the transistor10. The first layer adjacent to the surface 14- in the space between theregions 15 and I6 is a thin layer 22 of insulating material, such assilicon dioxide.

Deposited on this layer 22 of silicon dioxide is a layer 24 of materialwhich can accept charge carriers and confine them to localized sitesadjacent the interface between the layers 22 and 24. In this example,the layer 2% is a layer of silicon nitride which is itself an insulator.0n the silicon nitride layer 24 is a metallic electrode 26. Leads 2%, 30and 32, schematically shown, enable the application of externalpotentials to electrodes 18, 20 and 26. The conduction channel 34existing for depletion-type transistors with zero gate voltage applied,is shown by means of the dashed line 35.

The transistor Ml may be fabricated by known techniques. For example,the source and drain regions 15 and It may be formed by selectivelymasking the surface it and diffusing conductivity modifying substancesthrough spaced portions of the surface Ml into the body 12. The silicondioxide layer may be formed by thermally oxidizing the surface of thebody 12 or by the pyrolytic decomposition of an organic siloxanecompound such as tetraethdxysilane on the surface 14. The siliconnitride layer may be deposited by heating body 12 in an atmosphere ofsilane Sil-I and ammonia.

The insulating layer 24 is indicated as silicon nitride, but,equivalents having the same or similar properties may be substituted, ascircumstances may suggest or render expedient, without departing fromthe spirit or scope of the invention. Also, though transistor 10 isshown as a depletion-type semiconductor, an enhancement device, whetherof P-type or N-type silicon, having an insulator layer such as layer 24is also suitable for practicing the invention.

The memory action of transistor 10 can be demonstrated by measuring thecapacitance of the parallel plate system wherein the gate region 26 actsas one plate and the source 15 and drain 16 regions are connected to thesemiconductor body 12 which acts as the other plate thereof and in whichthe insulating and charge storing layers act as the dielectric thereof.When the gate potential is varied, this capacitance changes in themanner illustrated in FIG. 2, i.e., with a pronounced hysteresis loop.If the applied voltage is made sufficiently negative, the capacitancewill switch to a higher value and will remain in that state after theremoval of the negative voltage. If the potential applied to the gate ismade sufficie ntly positive, the capacitance is switched to the lowervalue and will remain that state after the removal of the positivevoltage.

Referring to FIG. 2, it should be noted that if the gate-tosourcevoltage is varied about the reference point (V by an amount whoseampliture is less than plus or minus one-half the amount AV, which may,for example, be 10 volts, the state of the transistor will beundisturbed! indicating a mode of operation, which will benondestructive of the information stored in the device.

The phenomenon just described is manifested by the device exhibiting abivalued threshold voltage when operated as a transistor. In contrast tothe change in capacitance, for an N- channel device, if the voltageapplied to the gate is made sufficiently more positive than the voltageat the source electrode, the threshold voltage (V will switch to a highvalue of threshold voltage (V- and if the applied voltage is madesufficiently negative with respect to the source and drain electrodes,the threshold voltage is switched to a low value of threshold voltage (VThe circuit of FIG. 3 is a logic gate whose threshold may be variedthereby controlling the passage of input signals. Transistor 50 is shownwith its gate electrode connected to terminal 52, its drain electrodeconnected to terminal 54 and its source electrode connected to referenceterminal 56. A resistor S8 is connected between terminal 54 and junctionpoint 60 and a source of potential 62 of magnitude V is connectedbetween junction point 60 and terminal 56. Terminal 54 serves as thevoltage output of the circuit while the signal across resistor 58 isindicative of the current flowing in the circuit. Potential source 62 isshown as a battery but it may instead be either pulsed, a half waverectified, or a full rectified power source.

A source of positive potential of magnitude V may be connected by meansof switch 66 to the gate 52 and a source of negative potential 68 ofmagnitude V may be connected by means of switch 70 to gate electrode 52.The gate terminal 52 is also connected to one terminal of capacitor 72,the other terminal of the capacitor being connected to signal generator74,. Switch 76, connected across capacitor 72, may be used to shunt outthe capacitor and to directly couple the signal generator 74 to the gateof transistor 50. Note that while for purposes of the presentexplanation, the switches are shown to be mechanical switches, inpractice they may be electronic devices such as field effect transistorsor bipolar devices.

The amplitudes V and V of potential sources 641 and 68 are madesufficiently large to permit the threshold of transistor fall to be setto either its low or high state. By way of example, for this particularcase, V and V may each be chosen to be equal to 22.5 volts (plus in onecase, minus in the other).

For depletion-type transistor 50, the closure of switch 66 applies apositive 22.5 volts potential to the gate electrode setting itsthreshold voltage to V which is approximately equal to 4 volts, asindicated by the voltage-current (V-I) characteristics shown in FIG. 4a.Note that with a gate voltage (V of zero volts, the drain current (I fora drain-to-source voltage (V greater than 4 volts is approximately 5 ma.Note also that the knee of the constant current curve for V 0corresponds to a value of 4 volts along the X axis (said axisrepresenting the value of drain-to-source (V voltage). Since the knee ofthe curve occurs at a point at which V is equal to the differencebetween the gate and threshold voltage (V V and since V is equal tozero, then obviously V is equal to approximately 4 volts. When switch 66is opened this value of V exhibited by transistor St) is maintained solong as any potential applied to the gate electrode does not reversebias the gate-to-source region by an amount exceeding the referencevalue, which in the case given by way of example is approximately 3volts about a negative bias of -7 volts.

Closing switch 70, while switch 66 is open applies a negative 22.5 voltspotential to the gate of transistor 50. Applying this large reverse biasbetween the gate and the source and drain electrodes of the device setsthe transistor into its low threshold state (V as indicated in FIG. 4!).FIG. db is essentially the same as FIG. 40 except that the thresholdlevel has been decreased by approximately 6 volts Note that in FIG. 4bthe curve traced for the condition when V equals 0, indicates that acurrent of 10 ma. is obtained along the flat portion of the curve andwith the knee of the curve corresponding to the drain-to-sourcepotential of 10 volts. The potential at which knee occurs, as explainedbefore, indicates that the threshold voltage of transistor 54) is now l0volts. Thus, by applying a negative potential between the gate andsource electrode, the threshold voltage has been changed from 4 volts tol0 volts. This value of threshold will be maintained even though switch70 is open and so long as any potential applied to the gate electrodedoes not forward bias the gate-to-source region by an amount exceedingthe value of the indicated reference voltage, which in the case given,by way of example, is approximately +3 volts about a negative bias of -7volts.

Thus, with transistor 50 in the V state any signal above -1 0 volts willcause conduction and result in an output signal. However, withtransistor 59 set to the V state, transistor 50 will be cut off to allsignals not exceeding -4 volts in amplitude. The threshold voltage isthus used to discriminate between signals of varying amplitudes. Animportant feature of the circuit of the present invention is that allpotentials may be removed from the transistor and it will remain in thestate in which it was last placed. This is of great value in memoryarrays as loss of power or other computer system malfunction of similarnature does not destroy the stored information.

FIG. 5 shows a flip-flop or memory circuit comprising transistor which,for this example, will be assumed to be an N-channel device of theenhancement type having a silicon nin'ide layer as described in FIG. I.The gate electrode of transistor b ll is shown connected to one side ofsignal generators 82 and 84, whose internal impedances are sufiicientlyhigh to prevent one generator from shorting the other and, the other endof said signal generators is connected to terminal Mid shown asreference or ground potential. Signal generator 86 is shown connectedbetween terminal Mill and the source electrode of transistor 86. Thedrain of transistor bl) is shown connected to resistor 88 at terminal90, which also serves as the output terminal; The other end of resistor88 is connected to the positive terminal of potential source $2 ofamplitude V the negative terminal of potential source 92 being connectedto terminal too.

As shown in FIG. 5, the amplitude of the signal from signal sources 84and $6 is bivalued being either zero volts or 22.5 volts. Withgenerators 86 and 82 at ground potential, a 22.5 volt pulse fromgenerator 84 forward biases the gate-to-source region of transistor 80setting the transistor to its high voltage V state, which for example,may be equal to +10 volts. A read pulse from generator 82 having a valuegreater than V but less than V applied to the gate of transistor 30 willnot be sufficient to overcome the value of threshold voltage and nosignal will be observed at terminal ill). Depending on the definition ofthe logic levels this condition may, for example, correspond to the setcondition of a flip-flop or the storing of a logic l or a logic 0" in amemory cell since the output voltage is maintained at +V and there is noconduction of current in the drain source path of transistor 80.

With signal generators 852 and 84 now returned to ground potential,signal generator 86 may be triggered to provide a positive pulse of 22.5volts amplitude to the source electrode. This pulse provides a reversebias to the source-gate region, which is analogous to the conditiondescribed in FIG. 3 when switch 70 was closed. This causes transistor 80to be set in the low threshold condition which, for example, may beequal to +4 volts. Now, a read signal from generator 82 having a valuegreater than V but less than V will cause current to flow between thedrain and source of transistor 80 resulting in a voltage other than V atterminal 9%. in keeping with the definition of logic level stated above,this state of the transistor may correspond to the reset condition of aflip-flop since the transistor is returned to the low threshold voltagestate. Note that, as shown in FIG. 6, the parallel combination ofgenerators 82 and 84 may be replaced by a DC source, whose maximumamplitude meets the requirements set for the maximum amplitude of pulsegenerator $2 placed in series with a pulse generator such as generator84.

Although the device of FIG. 1 and the circuits of FIGS. 3 and 5 employN-type conductivity transistors, it should be appreciated that P-typedevices may also be employed provided that the appropriate changes aremade in the connections of the bias sources and the levels of the inputsignals.

1 claim:

1. In combination:

a field effect transistor having source, drain and gate electrodes andof the type which in response to a first voltage of greater than a givenvalue applied between its gate and source electrodes in a direction toforward bias the gate with respect to the source exhibits a firstthreshold value and which in response to a second voltage of greaterthan a given value applied between its gate and source electrodes in adirection to reverse bias the gate with respect to the source exhibits asecond threshold value;

means coupled between said source and gate electrodes for selectivelyapplying one of said first and second voltages for establishing thethreshold setting of said transistor;

means coupled between said source and gate electrodes for selectivelyapplying thereto a read voltage of a value between said second thresholdvalue and said given value; and

means coupled to said transistor for sensing whether or not it conductscurrent in its source-to-drain path in response to said read voltage.

2. The combination as claimed in claim 1, wherein said transistor is aninsulated gate field efiect transistor.

3. The combination as claimed in claim 2, wherein said first thresholdvalue is greater in mamtitude than said second threshold value.

a. The combination as claimed in claim 3, wherein said read voltage isapplied in a direction to forward bias the gatewsource region andwherein the magnitude of said given value is less than the magnitude ofsaid first threshold value.

5. The combination as claimed in claim 4, wherein there is no conductionin response to said read voltage when the transistor is in the firstthreshold setting and wherein there is conduction in response to saidread voltage when the transistor is in the second threshold setting.

